Semiconductor structure and method of forming the same
US10580780B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 11, 2018 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Jun 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/035
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided is a semiconductor structure including a substrate, an isolation structure, a fuse and two gate electrodes. The isolation structure is located in the substrate and defines active regions of the substrate. The fuse is disposed on the isolation structure. The gate electrodes are disposed on the active regions and connected to ends of the fuse. In an embodiment, a portion of a bottom surface of the fuse is lower than top surfaces of the active regions of the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.