Pulsed level shifter circuitry
US10581412B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2019 |
| Grant date | Mar 3, 2020 |
| Priority date | — |
| Expiry date | Mar 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.