Flip flop of a digital electronic chip
US10585143B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Jul 10, 2018 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Aug 28, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3312
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A flip flop includes a data input, a clock input, a test chain input, a test chain output, a monitoring circuit, and an alert transmission circuit. The monitoring circuit is adapted to generate an alert if the time between arrival of a data bit and a clock edge is less than a threshold. The alert transmission circuit is adapted to apply during a monitoring phase an alert level to the test chain output in the event of an alert generated by the monitoring circuit, and to apply the alert level to the test chain output when an alert level is received at the test chain input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.