Method and apparatus for utilizing estimations for register retiming in a design compilation flow
US10586004B2 · kind B2 · utility
1Cited by
8References
20Claims
0Family size
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Key dates
| Filing date | Jun 22, 2015 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Sep 18, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for designing a system on a target device includes performing one of synthesis, placement, and routing on the system. A designer is presented with a timing analysis of the system after one of the synthesis, placement, and routing, wherein the timing analysis reflects register retiming optimizations predicted to be implemented on the system. One of the synthesis, placement, and routing is modified in response to input provided by the designer after the presenting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.