Dynamic bipolar write-assist for non-volatile memory elements
US10586581B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2018 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Nov 30, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Structures for a non-volatile memory and methods for forming and using such structures. A bitcell of the non-volatile memory includes a nonvolatile memory element and a field-effect transistor having a drain region coupled with the nonvolatile memory element, a source region, and a gate electrode. A word line is coupled with the gate electrode of the field-effect transistor, a bit line is coupled with the nonvolatile memory element, and a source line is coupled with the source region of the field-effect transistor. A power supply is configured to supply a negative bias voltage to the bit line in order to provide a first state for writing data to the nonvolatile memory element or to supply the negative bias voltage to the source line in order to provide a second state for writing data to the nonvolatile memory element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.