Patent · US Active

Via cleaning to reduce resistance

US10586732B2 · kind B2 · utility

4Cited by

11References

19Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Yann Mignot · Slingerlands, US
Chih-Chao Yang · Glenmont, US

Key dates

Filing date	Jun 30, 2016
Grant date	Mar 10, 2020
Priority date	—
Expiry date	Jul 23, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH01L23/53295
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method includes forming at least a first via in a multilayer structure comprising a first layer and a second layer formed over the first layer, the first via extending from a top of the second layer to a top of a first contact formed in the first layer and forming a polymer film on at least a portion of sidewalls of the first via by etching the top of the first contact using a cleaning process.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.