Clock distribution and generation architecture for logic tiles of an integrated circuit and method of operating same
US10587271B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 6, 2019 |
| Grant date | Mar 10, 2020 |
| Priority date | — |
| Expiry date | Jul 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17796
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.