Compressed scan chains with three input mask gates and registers
US10591540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 19, 2018 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Jun 8, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Electronic scan circuitry includes a decompressor (510), a plurality of scan chains (520.i) fed by the decompressor (510), a scan circuit (502, 504) coupled to the plurality of scan chains (520.i) to scan them in and out, a masking circuit (590) fed by the scan chains (520.i), and a scannable masking qualification circuit (550, 560, 580) coupled to the masking circuit (590), the masking qualification circuit (550, 560, 580) scannable by scan-in of bits by the decompressor (510) along with scan-in of the scan chains (520.i), and the scannable masking qualification circuit (550, 560, 580) operable to hold such scanned-in bits upon scan-out of the scan chains through the masking circuit (590). Other scan circuitry, processes, circuits, devices and systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.