Inventor · Bengaluru, IN

Prakash Narayanan

40Patents
6h-index
23Co-inventors
65Inventor score

Filing activity: Oct 14, 2010 → Feb 24, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US8887018B2 Masking circuit removing unknown bit from cell in scan chain Physics 16 Active
US9091729B2 Scan chain masking qualification circuit shift register and bit-field decoders Physics 10 Active
US10591540B2 Compressed scan chains with three input mask gates and registers Physics 7 Active
US9229055B2 Decompressed scan chain masking circuit shift register with log2(n/n) cells Physics 7 Active
US9081063B2 On-chip IR drop detectors for functional and test mode scenarios, circuits, processes and systems Physics 7 Active
US9952283B2 Compressed scan chains with three input mask gates and registers Physics 6 Active
US10184980B2 Multiple input signature register analysis for digital circuitry Physics 5 Active
US9791505B1 Full pad coverage boundary scan Physics 4 Active
US9823282B2 On-chip IR drop detectors for functional and test mode scenarios, circuits, processes and systems Physics 4 Active
US10579454B2 Delay fault testing of pseudo static controls Physics 4 Active
US10866280B2 Scan chain self-testing of lockstep cores on reset Physics 3 Active
US10331826B2 False path timing exception handler circuit Electricity 2 Active
US11073557B2 Phase controlled codec block scan of a partitioned circuit device Physics 2 Active
US8839063B2 Circuits and methods for dynamic allocation of scan test resources Physics 2 Active
US11119152B2 Functional circuitry, decompressor circuitry, scan circuitry, masking circuitry, qualification circuitry Physics 2 Active
US8972807B2 Integrated circuits capable of generating test mode control signals for scan tests Physics 2 Active
US10776546B2 False path timing exception handler circuit Electricity 1 Active
US11209481B2 Multiple input signature register analysis for digital circuitry Physics 1 Active
US10983161B2 Full pad coverage boundary scan Physics 1 Active
US10460821B2 Area efficient parallel test data path for embedded memories Physics 1 Active
US11592483B2 Compressed scan chain diagnosis by internal chain observation, processes, circuits, devices and systems Physics 1 Active
US10818374B2 Testing read-only memory using memory built-in self-test controller Physics 1 Active
US11073553B2 Dynamic generation of ATPG mode signals for testing multipath memory circuit Physics 1 Active
US11300615B2 Transistion fault testing of funtionally asynchronous paths in an integrated circuit Physics 1 Active
US11555853B2 Scan chain self-testing of lockstep cores on reset Physics 1 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.