Dynamic variable precision computation
US10592207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 8, 2019 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Apr 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/729
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A conversion unit converts operands from a conventional number system that represents each binary number in the operands as one bit to redundant number system (RNS) operands that represent each binary number as a plurality of bits. An arithmetic logic unit performs an arithmetic operation on the RNS operands in a direction from a most significant bit (MSB) to a least significant bit (LSB). The arithmetic logic unit stops performing the arithmetic operation prior to performing the arithmetic operation on a target binary number indicated by a dynamic precision associated with the RNS operands. In some cases, a power supply provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.