Patent · US Active

Very low precision floating point representation for deep learning acceleration

US10592208B2 · kind B2 · utility

5Cited by

2References

19Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Naigang Wang · Ossining, US
Kailash Gopalakrishnan · San Jose, US
Jungwook Choi · Seoul, KR
Silvia M. Mueller · Altdorf, DE
Ankur Agrawal · Sidhauli, IN
Daniel Brand · Cologne, DE

Key dates

Filing date	May 7, 2018
Grant date	Mar 17, 2020
Priority date	—
Expiry date	May 12, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F2207/4824
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A specialized circuit is configured for floating point computations using numbers represented by a very low precision format (VLP format). The VLP format includes less than sixteen bits and is apportion into a sign bit, exponent bits (e), and mantissa bits (p). The configured specialized circuit is operated to store an approximation of a numeric value in the VLP format, where the approximation is represented as a function of a multiple of a fraction, where the fraction is an inverse of a number of discrete values that can be represented using only the mantissa bits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.