Safety hypervisor function

US10592270B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Simon Brewerton · Trowbridge, GB
• Glenn Ashley Farrall · Long Ashton, GB
• Neil Hastie · Gloucester, GB
• Frank Hellwig · Wunstorf, DE
• Richard Knight · Deeping St James, GB
• Antonio Vilela · Mering, DE

Key dates

• Filing date: Oct 16, 2017
• Grant date: Mar 17, 2020
• Expiry date: Feb 2, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2009/45587
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The disclosure relates to systems and methods for defining a processor safety privilege level for controlling a distributed memory access protection system. More specifically, a safety hypervisor function for accessing a bus in a computer processing system includes a module, such as a Computer Processing Unit (CPU) or a Direct Memory Access (DMA) for accessing a system memory and a memory unit for storing a safety code, such as a Processor Status Word (PSW) or a configuration register (DMA (REG)). The module allocates the safety code to a processing transaction and the safety code is visible upon access of the bus by the module.