Instructions and logic to provide advanced paging capabilities for secure enclave page caches

US10592421B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Carlos V. Rozas · Portland, US
• Ilya Alexandrovich · Haifa, IL
• Ittai Anati · Ramat HaSharon, IL
• Alex Berenzon · Zichron Ya'akov, IL
• Michael A. Goldsmith · Lake Oswego, US
• Barry E. Huntley · Hillsboro, US
• Anton M. Ivanov · Moscow, RU
• Simon P. Johnson · Beaverton, US
• Rebekah M. Leslie-Hurd · Portland, US
• Francis X. McKeen · Portland, US
• Gilbert Neiger · Hillsboro, US
• Rinat Rappoport · Haifa, IL
• Scott Dion Rodgers · Hillsboro, US
• Uday Savagaonkar · Redmond, US
• Vincent R. Scarlata · Beaverton, US
• Vedvyas Shanbhogue · Austin, US
• Wesley H. Smith · Raleigh, US
• William Wood · Hillsboro, US

Key dates

• Filing date: Aug 29, 2016
• Grant date: Mar 17, 2020
• Expiry date: Aug 29, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/402
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Instructions and logic provide advanced paging capabilities for secure enclave page caches. Embodiments include multiple hardware threads or processing cores, a cache to store secure data for a shared page address allocated to a secure enclave accessible by the hardware threads. A decode stage decodes a first instruction specifying said shared page address as an operand, and execution units mark an entry corresponding to an enclave page cache mapping for the shared page address to block creation of a new translation for either of said first or second hardware threads to access the shared page. A second instruction is decoded for execution, the second instruction specifying said secure enclave as an operand, and execution units record hardware threads currently accessing secure data in the enclave page cache corresponding to the secure enclave, and decrement the recorded number of hardware threads when any of the hardware threads exits the secure enclave.