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US10592428B1 · kind B1 · utility
6Cited by
0References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 27, 2017 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Apr 6, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A translation buffer is provided in parallel to a translation lookaside buffer (TLB) to cache translations between intermediate physical addresses (IPAs) and pointers for entries in the TLB corresponding to the IPAs. The pointers can be used to identify and invalidate only certain entries in the TLB as compared to invalidating the whole TLB.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.