Read process in a semiconductor memory device including a memory cell transistor
US10593405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2018 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Aug 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory device includes: a word line; a first memory cell; a first circuit; and a second circuit. The first memory cell is connected to the word line. The first circuit generates a first voltage having a waveform including a first time period during which a voltage value increases with time and a second time period during which the voltage value decreases with time, and applies the generated first voltage to the word line. The second circuit measures first time from a first timing when a state of the first memory cell changes according to the first voltage to a second timing when the state of the first memory cell changes according to the first voltage after the first timing. The second circuit determines first data stored in the first memory cell on the basis of the measured first time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.