Selectively etched self-aligned via processes
US10593594B2 · kind B2 · utility
2Cited by
33References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2018 |
| Grant date | Mar 17, 2020 |
| Priority date | — |
| Expiry date | Dec 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1036
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a self-aligned via comprising recessing a first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is formed on the first insulating layer. A via is formed through the second insulating layer to one of the first conductive lines. Semiconductor devices comprising the self-aligned via and apparatus for forming the self-aligned via are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.