Systems and methods involving control-I/O buffer enable circuits and/or features of saving power in standby mode
US10599443B2 · kind B2 · utility
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12References
5Claims
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Key dates
| Filing date | Oct 18, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Oct 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2227
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a clock frequency detected control-i/o buffer enable circuit in a semiconductor device uses control I/O buffer enable circuitry and/or features of saving power in standby mode. The method may provide low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.