Admission control for memory access requests
US10599577B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2016 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Oct 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Managing memory access requests for a plurality of processor cores includes: storing admission control information for determining whether or not to admit a predetermined type of memory access request into a shared resource that is shared among the processor cores and includes one or more cache levels of a hierarchical cache system and at least one memory controller for accessing a main memory; determining whether or not a memory access request of the predetermined type made on behalf of a first processor core should be admitted into the shared resource based at least in part on the stored admission control information; and updating the admission control information based on a latency of a response to a particular memory access request admitted into the shared resource, where the updating depends on whether the response originated from a particular cache level included in the shared resource or from the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.