Superconducting quantum circuits layout design verification
US10599805B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2017 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Dec 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Verifying a quantum circuit layout design is provided. A qubit layout is received as input. The qubit layout is generated from a qubit schematic. The qubit schematic includes a plurality of qubits, a plurality of coupling buses, a plurality of readout buses, and a plurality of readout ports. Design rules checking is performed on the qubit layout input, using a predefined set of design rule. The bus style/frequency and qubit information are extracted from the qubit layout input. A new qubit schematic is generated from the extracted bus style/frequency and qubit information. The qubit layout is verified based on the new qubit schematic being the same as the qubit schematic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.