Multi-stack three-dimensional memory devices
US10600781B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 16, 2018 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Dec 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/01
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices having multiple memory stacks and methods for forming the 3D memory devices are disclosed. In an example, a 3D memory device includes a first device chip, a second device chip, and a bonding interface. The first device chip includes a peripheral device and a first interconnect layer. The second device chip includes a substrate, two memory stacks disposed on opposite sides of the substrate, two memory strings each extending vertically through one of the two memory stacks, and a second interconnect layer. The bonding interface is formed vertically between the first interconnect layer of the first device chip and the second interconnect layer of the second device chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.