Silicon PMOS with gallium nitride NMOS for voltage regulation
US10600787B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 28, 2016 |
| Grant date | Mar 24, 2020 |
| Priority date | — |
| Expiry date | Mar 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure pertains to a gallium nitride transistor that is formed in a trench etched into a silicon substrate. A gallium nitride layer is on the trench of the silicon substrate. A source electrode and a drain electrode reside on the gallium nitride layer. A gate electrode resides on the gallium nitride layer between the source electrode and the drain electrode. A first polarization layer resides on the gallium nitride layer between the source electrode and the gate electrode, and a second polarization layer resides on the gallium nitride layer between the gate electrode and the drain electrode. The silicon substrate can include a silicon 111 substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.