Test device for testing integrated circuit
US10605861B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Dec 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3177
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
The present invention discloses a test device for testing an integrated circuit. An embodiment of the test device includes an on-chip-clock controller (OCC), a pulse debugging circuit and a register circuit. The OCC is configured to generate an output clock according to an input clock, in which the output clock is for testing a circuitry under test (CUT) that is included in the test device. The pulse debugging circuit is configured to generate a pulse record according to a pulse number of the output clock, in which the pulse record is used to find out whether a test status dependent upon the output clock is abnormal. The register circuit is configured to store and output the pulse record according to a reliable clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.