Coherent interconnect power reduction using hardware controlled split snoop directories
US10606339B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2016 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Jul 4, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.