Philippe Boucard
28Patents
4h-index
14Co-inventors
60Inventor score
Filing activity: Dec 11, 1998 → Mar 19, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7574629B2 | Method and device for switching between agents | Physics | 19 | Active |
| US8316171B2 | Network on chip (NoC) with QoS features | Electricity | 6 | Active |
| US7769027B2 | Method and device for managing priority during the transmission of a message | Electricity | 5 | Active |
| US9225665B2 | Network on a chip socket protocol | Physics | 4 | Active |
| US8930638B2 | Method and apparatus for supporting target-side security in a cache coherent system | Physics | 3 | Active |
| US7148728B2 | Digital delay device, digital oscillator clock signal generator and memory interface | Electricity | 3 | Expired |
| US6516004B1 | HDLC digital data transmission protocol controller | Electricity | 2 | Expired |
| US8645557B2 | System of interconnections for external functional blocks on a chip provided with a single configurable communication protocol | Physics | 2 | Active |
| US8254380B2 | Managing messages transmitted in an interconnect network | Electricity | 2 | Active |
| US8441931B2 | Method and device for managing priority during the transmission of a message | Electricity | 2 | Active |
| US9465749B2 | DMA engine with STLB prefetch capabilities and tethered prefetching | Physics | 1 | Active |
| US9396130B2 | System translation look-aside buffer integrated in an interconnect | Physics | 1 | Active |
| US9141556B2 | System translation look-aside buffer with request-based allocation and prefetching | Physics | 1 | Active |
| US8824295B2 | Link between chips using virtual channels and credit based flow control | Physics | 1 | Active |
| US8788737B2 | Transport of PCI-ordered traffic over independent networks | Physics | 0 | Active |
| US10606339B2 | Coherent interconnect power reduction using hardware controlled split snoop directories | Emerging Cross-Sectional Technologies | 0 | Active |
| US9177615B2 | Power disconnect unit for use in data transport topology of network on chip design having asynchronous clock domain adapter sender and receiver each at a separate power domain | Emerging Cross-Sectional Technologies | 0 | Active |
| US7755920B2 | Electronic memory device | Physics | 0 | Active |
| US12332811B1 | Method and apparatus for exclusive access fairness in memory systems with distributed exclusive access management | Physics | 0 | Active |
| US9172656B2 | Method and device for managing priority during the transmission of a message | Electricity | 0 | Active |
| US9069912B2 | System and method of distributed initiator-local reorder buffers | Physics | 0 | Active |
| US8031730B2 | System and method for transmitting a sequence of messages in an interconnection network | Electricity | 0 | Active |
| US9049124B2 | Zero-latency network on chip (NoC) | Emerging Cross-Sectional Technologies | 0 | Active |
| US11940939B2 | Encoding byte information on a data bus with separate code | Physics | 0 | Active |
| US7639704B2 | Message switching system | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.