Scheduling tasks in a multi-threaded processor
US10606641B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 19, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Oct 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4881
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor comprising: an execution unit for executing a respective thread in each of a repeating sequence of time slots; and a plurality of context register sets, each comprising a respective set of registers for representing a state of a respective thread. The context register sets comprise a respective worker context register set for each of the number of time slots the execution unit is operable to interleave, and at least one extra context register set. The worker context register sets represent the respective states of worker threads and the extra context register set being represents the state of a supervisor thread. The processor is configured to begin running the supervisor thread in each of the time slots, and to enable the supervisor thread to then individually relinquish each of the time slots in which it is running to a respective one of the worker threads.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.