Memory system and operating method thereof
US10606689B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes: an ECC unit suitable for generating third data by correcting second data and a third DBI flag by correcting a second DBI flag, based on the second data, the second DBI flag, and a second parity, which are provided through a channel; a DBI unit suitable for generating fourth data by determining whether a plurality of third data bits respectively corresponding to a plurality of DBI flag bits constituting the third DBI flag are inverted, based on the third data and the third DBI flag; and a DM unit suitable for generating a DM flag indicating whether a write operation is performed on a plurality of fourth data bits constituting the fourth data, based on the second data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.