Patent · US Active

Sharing virtual and real translations in a virtual cache

US10606762B2 · kind B2 · utility

1Cited by

14References

4Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Markus Helms · Eppelheim, DE
Christian Jacobi · West Park, US
Martin Recktenwald · Eppelheim, DE
Johannes C. Reichart · Highland, US

Key dates

Filing date	Jun 16, 2017
Grant date	Mar 31, 2020
Priority date	—
Expiry date	Jun 16, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/68
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Disclosed herein is a virtual cache directory in a processor that eliminates address translations when the virtual address and the real address in the cache directory are the same. The processor is configured to support virtual memory and multiple threads. The virtual cache directory includes a plurality of directory entries, each entry is associated with a cache line. Each cache line has a tag. The tag includes a logical address, an address space identifier, a real address bit indicator, and virtual address to real address indicator. This virtual address to real address indicator indicates if the logical address and the real address are the same. When activated, address translation is not performed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.