Markus Helms
39Patents
3h-index
37Co-inventors
63Inventor score
Filing activity: Jul 6, 2001 → Aug 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6952739B2 | Method and device for parameter independent buffer underrun prevention | Physics | 8 | Expired |
| US6874105B2 | Operation graph based event monitoring system | Physics | 7 | Expired |
| US10380033B2 | Multi-engine address translation facility | Physics | 5 | Active |
| US7337240B2 | Virtualization of I/O adapter resources | Physics | 3 | Expired |
| US10417252B2 | Optimizing data conversion using pattern frequency | Physics | 2 | Active |
| US7466716B2 | Reducing latency in a channel adapter by accelerated I/O control block processing | Electricity | 2 | Active |
| US10303759B2 | Memory preserving parse tree based compression with entropy coding | Electricity | 2 | Active |
| US11775445B2 | Translation support for a virtual cache | Emerging Cross-Sectional Technologies | 1 | Active |
| US9589087B2 | Verification environments utilizing hardware description languages | Physics | 1 | Active |
| US10380032B2 | Multi-engine address translation facility | Physics | 1 | Active |
| US9898348B2 | Resource mapping in multi-threaded central processor units | Physics | 1 | Active |
| US10083124B1 | Translating virtual memory addresses to physical addresses | Physics | 1 | Active |
| US10606762B2 | Sharing virtual and real translations in a virtual cache | Physics | 1 | Active |
| US10353825B2 | Suspending translation look-aside buffer purge execution in a multi-processor environment | Physics | 0 | Active |
| US11308277B2 | Memory preserving parse tree based compression with entropy coding | Electricity | 0 | Active |
| US10353828B2 | Zone-SDID mapping scheme for TLB purges | Emerging Cross-Sectional Technologies | 0 | Active |
| US7818459B2 | Virtualization of I/O adapter resources | Physics | 0 | Active |
| US10698835B2 | Suspending translation look-aside buffer purge execution in a multi-processor environment | Physics | 0 | Active |
| US9886327B2 | Resource mapping in multi-threaded central processor units | Physics | 0 | Active |
| US9703909B2 | Verification environments utilizing hardware description languages | Physics | 0 | Active |
| US10140217B1 | Link consistency in a hierarchical TLB with concurrent table walks | Emerging Cross-Sectional Technologies | 0 | Active |
| US10915547B2 | Optimizing data conversion using pattern frequency | Physics | 0 | Active |
| US12141076B2 | Translation support for a virtual cache | Emerging Cross-Sectional Technologies | 0 | Active |
| US10353827B2 | Zone-SDID mapping scheme for TLB purges | Emerging Cross-Sectional Technologies | 0 | Active |
| US10387326B2 | Incorporating purge history into least-recently-used states of a translation lookaside buffer | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.