Patent · US Active

Clock signal monitor for slave device on a master-slave bus

US10606794B1 · kind B1 · utility

4Cited by

5References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Benjamin Kollmitzer · Graz, AT
Filippo Grillotti · Villach, AT
Richard Heinz · Munich, DE
Stephan LEISENHEIMER · Deisenhofen, DE

Key dates

Filing date	May 14, 2019
Grant date	Mar 31, 2020
Priority date	—
Expiry date	May 14, 2039

Classification

Technology area (CPC G)Physics
CPC primaryG06F13/4295
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A slave device may receive a clock signal from a master device via a bus. The slave device may detect a first pulse of the clock signal. The first pulse indicates that a bit is to be written to a slave shift register of the slave device. The slave device may identify a timeout threshold associated with the clock signal. The slave device may determine that the timeout threshold expired without a second pulse from the clock signal being detected. The slave device may reset, based on the timeout threshold expiring, the slave shift register to synchronize the slave shift register with a master shift register of the master device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.