Package substrate for a semiconductor package having landing pads extending toward a through-hole in a chip mounting region
US10607905B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2019 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Jun 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a package substrate including at least one through-hole in a chip mounting region, a plurality of wiring patterns at a top surface of the package substrate. The wiring patterns include respective extension portions and respective landing pads. At least some of the landing pads obliquely extend toward the through-hole. Conductive bumps are formed on corresponding landing pads to connect to a semiconductor chip mounted on the chip mounting region of the package substrate. A molding material extends between the top surface of the package substrate and the semiconductor chip and fills the through-hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.