Kun-dae Yeom
11Patents
4h-index
18Co-inventors
53Inventor score
Filing activity: Apr 29, 2004 → Jun 14, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7391105B2 | Unit semiconductor chip and multi chip package with center bonding pads and methods for manufacturing the same | Electricity | 140 | Expired |
| US8723333B2 | Semiconductor package including multiple chips and separate groups of leads | Electricity | 37 | Active |
| US8901750B2 | Semiconductor package including multiple chips and separate groups of leads | Electricity | 9 | Active |
| US8664757B2 | High density chip stacked package, package-on-package and method of fabricating the same | Electricity | 7 | Active |
| US8193626B2 | Semiconductor package including multiple chips and separate groups of leads | Electricity | 2 | Active |
| US7759795B2 | Printed circuit board having reliable bump interconnection structure, method of fabricating the same, and semiconductor package using the same | Emerging Cross-Sectional Technologies | 1 | Active |
| US10361135B2 | Semiconductor package including landing pads extending at an oblique angle toward a through-hole in the package substrate | Electricity | 1 | Active |
| US10607905B2 | Package substrate for a semiconductor package having landing pads extending toward a through-hole in a chip mounting region | Electricity | 1 | Active |
| US7521289B2 | Package having dummy package substrate and method of fabricating the same | Electricity | 1 | Expired |
| US9041181B2 | Land grid array package capable of decreasing a height difference between a land and a solder resist | Emerging Cross-Sectional Technologies | 0 | Active |
| US9455217B2 | Semiconductor package including multiple chips and separate groups of leads | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.