Integrated DRAM with low-voltage swing I/O
US10607977B2 · kind B2 · utility
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Key dates
| Filing date | Oct 18, 2017 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Oct 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/157
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This document describes apparatuses and techniques for integrated DRAM with low-voltage swing I/O. In some aspects, a dynamic random access memory (DRAM) die and application processor (AP) die are mounted to a system-in-package (SiP) die carrier that includes one or more redistribution layers. The DRAM die and AP die are located adjacent to each other on the die-carrier such that respective memory inputs/outputs of each die are proximate the other inputs/outputs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.