3-dimensional NOR memory array architecture and methods for fabrication thereof
US10608011B2 · kind B2 · utility
21Cited by
12References
21Claims
0Family size
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Key dates
| Filing date | Jun 19, 2018 |
| Grant date | Mar 31, 2020 |
| Priority date | — |
| Expiry date | Jun 29, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31111
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.