Scott Brad Herner
124Patents
15h-index
36Co-inventors
86Inventor score
Filing activity: Sep 13, 1999 → Jul 9, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8088688B1 | p+ polysilicon material on aluminum for non-volatile memory device and method | Electricity | 94 | Active |
| US8168506B2 | On/off ratio for non-volatile memory device and method | Electricity | 79 | Active |
| US8394670B2 | Vertical diodes for non-volatile memory device | Electricity | 76 | Active |
| US8659003B2 | Disturb-resistant non-volatile memory device and method | Electricity | 60 | Active |
| US10431596B2 | Staggered word line architecture for reduced disturb in 3-dimensional NOR memory arrays | Electricity | 59 | Active |
| US8187945B2 | Method for obtaining smooth, continuous silver film | Electricity | 59 | Active |
| US8198144B2 | Pillar structure for memory device and method | Electricity | 59 | Active |
| US8258020B2 | Interconnects for stacked non-volatile memory device and method | Electricity | 58 | Active |
| US10622377B2 | 3-dimensional NOR memory array with very fine pitch: device and method | Electricity | 52 | Active |
| US6429126B1 | Reduced fluorine contamination for tungsten CVD | Electricity | 47 | Expired |
| US6541401B1 | Wafer pretreatment to decrease rate of silicon dioxide deposition on silicon nitride compared to silicon substrate | Electricity | 47 | Expired |
| US8399307B2 | Interconnects for stacked non-volatile memory device and method | Electricity | 40 | Active |
| US8993397B2 | Pillar structure for memory device and method | Electricity | 21 | Active |
| US10608011B2 | 3-dimensional NOR memory array architecture and methods for fabrication thereof | Electricity | 21 | Active |
| US6635556B1 | Method of preventing autodoping | Emerging Cross-Sectional Technologies | 19 | Expired |
| US8426306B1 | Three dimension programmable resistive random accessed memory array with shared bitline and method | Physics | 14 | Active |
| US6303480A | Silicon layer to improve plug filling by CVD | Electricity | 14 | Expired |
| US8404553B2 | Disturb-resistant non-volatile memory device and method | Electricity | 10 | Active |
| US6639312B2 | Dummy wafers and methods for making the same | Emerging Cross-Sectional Technologies | 10 | Expired |
| US8697533B2 | Method for obtaining smooth, continuous silver film | Electricity | 9 | Active |
| US9252191B2 | Seed layer for a p+ silicon germanium material for a non-volatile memory device and method | Electricity | 7 | Active |
| US11309331B2 | 3-dimensional NOR memory array architecture and methods for fabrication thereof | Electricity | 6 | Active |
| US9246089B2 | Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states | Physics | 5 | Active |
| US8450209B2 | p+ Polysilicon material on aluminum for non-volatile memory device and method | Electricity | 5 | Active |
| US8815696B1 | Disturb-resistant non-volatile memory device using via-fill and etchback technique | Electricity | 5 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.