Patent · US Active

Hierarchical partial reconfiguration for programmable integrated circuits

US10608641B2 · kind B2 · utility

6Cited by

18References

7Claims

0Family size

Assignee

XILINX, INC. · US

Inventors

Hao Yu · Beijing, CN
Raymond Kong · San Jose, US
Brian S. Martin · Longmont, US
Jun Liu · 红钢城街道, CN

Key dates

Filing date	Jul 20, 2018
Grant date	Mar 31, 2020
Priority date	—
Expiry date	Jul 20, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG06F15/7867
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Hierarchical partial reconfiguration for integrated circuits includes converting, using computer hardware, a first partial reconfiguration module of a circuit design into a first partial reconfiguration container, wherein the circuit design is placed and routed, loading, using the computer hardware, a first netlist into the first partial reconfiguration container, wherein the first netlist includes a first plurality of partial reconfiguration modules that are initially empty, and including, using the computer hardware, a further netlist within each of the first plurality of partial reconfiguration modules. Using the computer hardware, the first partial reconfiguration container is implemented with the first plurality of partial reconfiguration modules being implemented within the first partial reconfiguration container.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.