Apparatus comprising a semiconductor arrangement
US10613136B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2018 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Jul 9, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/131
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising: a substrate; an integrated circuit region formed in the substrate; a seal ring disposed in the substrate to form a ring around the integrated circuit region, the seal ring configured to provide for protection against one or more of moisture ingress and ion ingress to the integrated circuit region and crack propagation through the substrate; and a defect sensor comprising a conductive track formed of at least one conductive layer in the substrate, the conductive track disposed outwardly of the seal ring and arranged to at least partially surround the integrated circuit region and seal ring, the conductive track having a first end terminal and a second end terminal to receive a detection signal therebetween to pass through the conductive track to detect a break in the conductive track and thereby a defect in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.