Patent · US Active

Apparatus and method for implementing bounding volume hierarchy (BVH) operations on tesselation hardware

US10614611B2 · kind B2 · utility

8Cited by

0References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Carsten Benthin · Großrosseln, DE
Gabor Liktor · San Francisco, US

Key dates

Filing date	Apr 7, 2017
Grant date	Apr 7, 2020
Priority date	—
Expiry date	Apr 7, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06T15/005
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus and method are described for using tessellation hardware to generate bounding volume hierarchies (BVHs) and perform other ray tracing operations. For example, one embodiment of an apparatus comprises: a shader to output a plurality of tessellation factors and one or more input surfaces; and a tessellation circuit comprising first circuitry and/or logic to tesselate each input surface to generate a new set of primitives and second circuitry and/or logic to concurrently generate a bounding volume hierarchy (BVH) based on the new set of primitives.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.