Memory system for controlling read voltage using cached data and operation method of the same
US10614880B2 · kind B2 · utility
2Cited by
1References
14Claims
0Family size
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Key dates
| Filing date | Dec 5, 2017 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Dec 5, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes: a memory device; a cache memory suitable for caching a portion of a data stored in the memory device; and a read voltage controller suitable for controlling a level of a read voltage of the memory device by comparing a cache data in the cache memory with a data from the memory device corresponding to the cache data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.