Patent · US Active

Method for removing barrier layer for minimizing sidewall recess

US10615073B2 · kind B2 · utility

0Cited by

7References

13Claims

0Family size

Assignee

ACM RESEARCH (SHANGHAI), INC. · CN

Inventors

Zhaowei Jia · Shanghai, CN
Jian Wang · Rosharon, US
Hui Wang · Shanghai, CN

Key dates

Filing date	Feb 15, 2015
Grant date	Apr 7, 2020
Priority date	—
Expiry date	Mar 15, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L22/20
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Provided is a method for removing barrier layer for minimizing sidewall recess. The method comprises the following steps: introduce noble-gas-halogen compound gas and carrier gas into an etching chamber within which a thermal gas phase etching process is being performed for etching a barrier layer (206) on non-recessed areas of an interconnection structure (501); detect an end point of the thermal gas phase etching process (502), if the thermal gas phase etching process reaches the end point end point, then execute the next step; if the thermal gas phase etching process doesn't reach the end point, then return to the previous step; stop introducing the noble-gas-halogen compound gas and the carrier gas to the etching chamber (503).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.