Self-aligned via

US10615117B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Kevin Lin · Beaverton, US
• Robert L. Bristol · Portland, US
• Rami Hourani · Santa Clara, US
• James M. Blackwell · Portland, US

Key dates

• Filing date: Dec 29, 2016
• Grant date: Apr 7, 2020
• Expiry date: Dec 29, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76897
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

There is disclosed in an example an integrated circuit, including: a first layer having a dielectric, a first conductive interconnect and a second conductive interconnect; a second layer having a third conductive interconnect; a conductive via between the first layer and the second layer to electrically couple the second conductive interconnect to the third conductive interconnect; a dielectric plug disposed vertically between the first layer and second layer and disposed to prevent the via from electrically shorting to the first conductive interconnect; and a dielectric cap covering the dielectric plug.