Integrated circuit multichip stacked packaging structure and method
US10615151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2016 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Nov 30, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/351
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit multichip stacked packaging structure and method, including: first pins, provided at bottom surface of first chip; second pins, provided at top surface of second chip; circuit layers, provided at top surface of substrate, and/or circuit layers, provided at bottom surface of substrate, and/or circuit layers, provided within substrate; first chip, provided at top surface of substrate; second chip, provided at top surface of first chip; first pin is electrically connected at least to one of circuit layers provided with circuit pins, substrate is provided with connecting through hole, which is docked with circuit pin, first opening thereof is docked with first pin, second opening thereof is operating window, electrically-conductive layer is provided within connecting through hole, and electrically connects first pin to circuit pin; second pin is electrically connected at least to one of circuit layers; second pin is electrically connected to circuit layer via electrically-conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.