Apparatuses and methods for compensating phase fluctuations
US10615953B2 · kind B2 · utility
1Cited by
2References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2017 |
| Grant date | Apr 7, 2020 |
| Priority date | — |
| Expiry date | Jan 26, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/123
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to methods and apparatuses for compensating carrier or clock signal phase fluctuations. An apparatus comprises a digital phase locked loop (210) comprising a phase error output (214) for a phase error (216) between a reference signal (218) and an output signal (212) generated by the digital phase locked loop, and a phase rotator (220) coupled to the phase error output (214) and configured to rotate a phase of a data signal based on the phase error (216).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.