Auto address generation for switch network
US10621132B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2017 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Aug 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/4004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments herein describe techniques for assigning address ranges to ports in switches forming a packet protocol switch network in an integrated circuit. Instead of relying on a designer to provide the addresses, the integrated circuit can include an address bus which is incremented as addresses are assigned to the ports. In one embodiment, the port addresses are assigned from a root device and defines the address range of each branch port and the address of each endpoint in the network. As the address bus reaches an endpoint, an adder in the endpoint increments the value of the address bus (e.g., the current address). The address bus may use serial or parallel data communication to assign the addresses. In another embodiment, instead of using a separate address bus, a data bus typically used for packet communication assigns the addresses to the ports in the network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.