Classification and localization of hotspots in integrated physical design layouts
US10621302B2 · kind B2 · utility
4Cited by
4References
17Claims
0Family size
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Key dates
| Filing date | Jun 27, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2038 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems for fabricating an integrated circuit include training a machine learning model using a training set that includes known physical design layout patterns that are classified according to whether the patterns include a hotspot. It is determined whether an input physical design layout pattern includes a hotspot using the machine learning model. A hotspot localization is generated for the input physical design layout patterns. The input physical design pattern is adjusted to cure the hotspot. A circuit is fabricated in accordance with the adjusted input physical design layout pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.