Block based non-maximum suppression
US10621464B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2019 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Jun 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06V10/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an interface and a processor. The interface may be configured to receive an array of scores. The processor may be configured to (i) parse the array of scores into a data flow including one or more operators, (ii) schedule the operators in one or more data paths, (iii) divide the array of scores into blocks of two or more scores by processing the array of scores using the one or more data paths, (iv) compute per-block information using the one or more data paths, and (v) compute local maxima position information for the array of scores by performing block based non-maximum suppression based on the per-block information using the one or more data paths. The data paths are generally implemented with a plurality of hardware circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.