Patent · US Active

Memory hold margin characterization and correction circuit

US10622044B2 · kind B2 · utility

1Cited by

7References

21Claims

0Family size

Assignee

QUALCOMM Incorporated · US

Inventors

Bipin Duggal · Delhi, IN
Naishad Narendra Parikh · Bengaluru, IN
Ritu Chaba · San Diego, US

Key dates

Filing date	Dec 14, 2017
Grant date	Apr 14, 2020
Priority date	—
Expiry date	Dec 14, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH03K5/131
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus including a memory subsystem. The memory subsystem includes a data input and a clock input. The apparatus also includes a variable delay circuit coupled to one of the data input or the clock input. Additionally, the apparatus includes a controller coupled to the variable delay circuit. The controller is configured to dynamically control the delay of the variable delay circuit. The controller may adjust the delay of the variable delay circuit based on at least one of timing data for a memory subsystem design of the memory subsystem, timing data for the memory subsystem, a voltage applied to the memory subsystem, or a temperature of the memory subsystem.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.