Memory cell and methods thereof
US10622051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Sep 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D48/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to various embodiments, a memory cell may include: a field-effect transistor structure comprising a channel region and a gate structure disposed at the channel region, the gate structure comprising a gate electrode structure and a gate isolation structure disposed between the gate electrode structure and the channel region; and a memory structure comprising a first electrode structure, a second electrode structure, and at least one remanent-polarizable layer disposed between the first electrode structure and the second electrode structure; wherein the first electrode structure of the memory structure is electrically conductively connected to the gate electrode structure of the field-effect transistor structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.