Phase change memory device with reduced read disturb and method of making the same
US10622063B2 · kind B2 · utility
1Cited by
8References
16Claims
0Family size
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Key dates
| Filing date | Jun 27, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Jun 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/882
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of operating a phase change memory device includes flowing a write current of a first polarity through a phase change memory element of a selected phase change memory cell, and flowing a read current of a second polarity opposite to the first polarity through the phase change memory element of the selected phase change memory cell. A first junction between the phase change memory element and a first electrode and a second junction between the phase change memory element and a second electrode exhibit asymmetric thermoelectric heat generation during the step of flowing the write current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.