Multi terminal capacitor within input output path of semiconductor package interconnect
US10622299B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2019 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Feb 7, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) device, e.g., wafer, chip, die, interposer, carrier, etc., includes a patterned mask that includes a first opening that exposes a signal region of a first contact. The mask further includes a second opening that exposes a signal region of a second contact that neighbors the first contact. The mask further includes a first capacitor tab opening that extends from the first opening toward the second contact and further exposes an extension region of the first contact. The mask further includes a second capacitor tab opening that extends from the second opening toward the first contact and further exposes an extension region of the second contact. A multi terminal capacitor may be connected to the IC device such that a first terminal is connected to the extension region of the first contact and a second terminal is connected to the extension region of the second contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.