3-dimensional NOR memory array with very fine pitch: device and method
US10622377B2 · kind B2 · utility
52Cited by
3References
46Claims
0Family size
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Key dates
| Filing date | Dec 21, 2018 |
| Grant date | Apr 14, 2020 |
| Priority date | — |
| Expiry date | Dec 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.